An Analysis on Various Implemented Scan Insertion Techniques that Reduces the Test Application Time
Maharshi Patel
PIT, Parul University, Vadodara, India , IN
Yogesh Parmar
PIT, Parul University, Vadodara, India , IN
Chintan Panchal
PIT, Parul University, Vadodara, India , IN
Keywords: VLSI, ATPG, DFT, Skip-Scan, Broadcast Scan
Abstract
As VLSI technology is continuously moving to lower technology nodes we need efficient technique for testing [7]. However, reliability and testability will main remain concerned for DFT in today’s VLSI design [7]. ATE machines are very expensive. i.e., more number of test patterns will result in more cost. The method of reduction the test application time thereby reducing the number of test patterns will result in reduction of test cost. So, reduction in testing time is must needed because it can makes DFT operation cheaper. In this analysis, we reviewed on an implemented test pattern reordering method by skipping of scan-chain architecture [1] and broadcast based on deterministic pattern generation algorithm [2] is reviewed. Test compression and pattern simulation method, logic cluster controllability and stitching method for reducing the overall test time. In this we are using ATPG tool for generating test patterns.
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