🕔 Call For Paper — Vol. 12  |  Issue 4  |  December 2026  |  Deadline: 20-Dec-2026
Track Paper Submit Paper Contact

Paper Details

Home › Archives › Paper Details
← Back to Issue
Vol. 4  No. 6 (2018) · Articles

Realisation of a Delta-Sigma Data converter with Lower Proportion of Oversampling

Santosh Kumar.B
CSE Department, New Horizon College of Engineering , IN

📅 Published: June 2018

Keywords: Delta-Sigma, Oversampling, Quantize, Digital Converter, Analog Converter.

📄 View / Download PDF ⬇ Download

Abstract

This paper centres around the plan of a single stage Delta-Sigma data converter with extremely low oversampling proportion for the remote application. Delta-Sigma data converters are utilized for low recurrence applications due to the point of confinement of the testing recurrence. One strategy for expanding the flag data transfer capacity of a sigma-delta ADC is to suitably exchange interior quantization with oversampling proportion. This paper investigates the conceivable advantages of applying the internal quantization with an extensive number of bits to a single stage Delta-Sigma data converter to decrease the oversampling proportion. A model chip with 8-bit internal quantization was created to show the execution of this approach.

How to Cite

Santosh Kumar.B, “Realisation of a Delta-Sigma Data converter with Lower Proportion of Oversampling,” International Journal of Technical Innovation in Modern Engineering & Science, vol. 4, no. 6, pp. 1404-1407, June 2018.

References

NA

🔒 Content is protected — © IJTIMES