Analysis on Different Metal Strategies for Clock Tree Synthesis
Repudi Veerendra Kumar
M.tech. VLSI & EMBEDDED,student,LBRCE,mylavaram,Vijayawada. , IN
Gummididala Venkata Rao
M.tech. VLSI & EMBEDDED,student,LBRCE,mylavaram,Vijayawada. , IN
Keywords: CTS, ROUTING, STA, VLSI, PHYSICAL DESIGN
Abstract
Clock Tree Synthesis is playing a vital role in physical design, distributing clock nets to all the sync points and balancing skew and insertion delay at the same instance to meeting the time. To balance insertion delay and skew, different methods will follow like adding buffers, inverters, up sizing, down sizing cells in the clock network. For routing these clock tree also we can use different metal strategies for balancing skew and insertion delay This paper mainly analyses that how the clock tree effect for different metal strategies utilized for routing and effect on skew and insertion delay by using the tool CADENCE ENCOUNTER.
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