ANALYSIS OF RADIX 2^4 SDF PIPELINE FFT ARCHITECTURE

Abstract

This paper describes the implementation of a R24 SDF Pipeline FFT Architecture using hardware description language Verilog HDL simulated up to 1 MHz for transformation length 16-point. A hardware oriented radix-24 algorithm is derived by integrating a twiddle factor in the folded transformation technique. The single-path delay feedback architecture is used to exploit the spatial regularity in signal flow graph of an algorithm [7]. For length-N DFT computation, the hardware requirement of proposed architecture is minimal on both dominant components: log4N-1 complex multipliers and N-1 complex data memory. In this paper, we present a 16-point FFT module, which reduces the multiplicative complexity by using both real and complex constant multiplications. In order to reduce the hardware complexity pruning technique is used.