DLL BASED MONTGOMERY MODULAR MULTIPLICATION

Abstract

Montgomery modular multiplication is rapidly used in cryptographic algorithms and DSP applications. The main objective of this paper is to lessen the delay and area of the multipliers while maintaining less hardware complexity. To speed up, high-speed Montgomery modular multiplication algorithms and hardware architectures employed which increases hardware complexity. This paper describes Design and Implementation of Dual Level Logic(DLL) based Montgomery modular multiplication on FPGA. This proposed, designed architecture provides 42.206ns of delay and occupies 4% of the total memory on FPGA. This architecture has been modeled with Verilog in Xilinx ISE Design Suite 14.7.