Design and Implementation of Custom Logic for utilizing DDR 2 Memory Controller on FPGA for High Speed Data Storage Application

Authors

  • Rikin J Nayak Assistant Professor, E&C Department, Chandubhai S. Patel Institute of Technology, Charotar University of Science & Technology, Changa, Gujarat
  • Jaiminkumar B Chavda Assistant Professor, IT Department, L.D. Collge of Engineering, Ahmedabad
  • Kishan Patel Assistant Professor, EE Department, Chandubhai S. Patel Institute of Technology, Charotar University of Science & Technology, Changa, Gujarat

Keywords:

FPGA, DDR2, Memory Controller, High Speed Data, RS232 protocol.

Abstract

In the recent development semiconductor technology and availability of microprocessors with rich instruction sets, FPGAs and other such computing platforms, many complex processing tasks becomes more easy, faster and accurate. With rich processing capabilities, it requires to have platform where large amount of data can be buffered for faster processing by high performance computing platforms. For optimized High performance, computing platform requires compatible memory interface, which enables the processing unit (microprocessor / FPGA) to communicate for data readout and write back at relatively faster speed which matches the processing speed. For storage, many different storage options are available like SRAM, DDR RAM, SDCARD, Flash Memory etc. Each one them has their own throughput for reading-writing. In this paper, A DDR2 memory controller is custom configured for High-speed data storage using Xilinx ISE tool and Virtex 5 FPGA as a computing platform. Detailed results are discussed in paper.

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Published

2021-11-19

How to Cite

J Nayak, R., B Chavda, J., & Patel, K. (2021). Design and Implementation of Custom Logic for utilizing DDR 2 Memory Controller on FPGA for High Speed Data Storage Application. International Journal of Technical Innovation in Modern Engineering & Science, 4(6), 939–944. Retrieved from https://ijtimes.com/index.php/ijtimes/article/view/1819