Design of Efficient 32-bit Low power Variable Latency Parallel Prefix BrentKung Adder

Abstract

A variable latency adder pays speculations in arithmetic circuits can replaced with appropriate one, which will produces faster and correct results. This paper proposes a novel variable latency adder based on Brent-Kung Parallel-Prefix topology that resulted more effective than variable latency Kogge-Stone and Han-Carlson parallelprefix topology. The proposed adder has two stages of operations, Pre-processing stage and Generation stage. The pre-processing stage of the design has propagate and generate circuits. Generation stage focuses on the carry generation and final result and the performance of the Brent-Kung adder through black cell takes large area. So, Gray cell can be replaced in its place of black cell which gives the Efficiency in Brent-Kung Adder. Finally, a new approach to design of efficient 32 bit low power variable latency parallel prefix Brent Kung Adder (BKA) concentrates on gate levels to improve the increase and decreases the memory. The Proposed Adder which gives the addition operation offers great advantages in reducing delay. Brent-Kung adder mostly used for low-power Designs and in this paper implementation of Brent-Kung Adder synthesized using Xilinx ISE 14.7 has been modelled with VHDL.