Design And Comparison Of Low Power Static RAM Using Cadence Tool In 180nm And 45nm Technology

Authors

  • Alka Deepak Dept.of ECE &Sahyadri College of Engineering and Management
  • Ann Thomas Dept.of ECE &Sahyadri College of Engineering and Management
  • Hemashree Dept.of ECE &Sahyadri College of Engineering and Management
  • Megha C Dept.of ECE &Sahyadri College of Engineering and Management
  • Megha N Dept.of ECE & Sahyadri College of Engineering and Management

Keywords:

SRAM, CMOS, Cadence, Low Power, 180nm Technology, 45nm Technology

Abstract

In the modern technology the demand for low power gadgets has been increasing massively. The fast growth of portable battery-operated gadgets has made lower power design an important factor. In this paper, the different architectures of SRAMs are designed and the performance of each cells are tested. A comparative study is made on the delay and power dissipation. The different architectures like 6T, 7T ,8T and 9T are considered for the purpose. These cells are designed using the generic process development kit (gpdk) 180nm and 45nm technologies. The cadence-virtuoso tool is used for designing and conducting the power analysis.

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Published

2019-05-01

How to Cite

Deepak, A. ., Thomas, A. ., Hemashree, Megha C, & Megha N. (2019). Design And Comparison Of Low Power Static RAM Using Cadence Tool In 180nm And 45nm Technology. International Journal of Technical Innovation in Modern Engineering & Science, 5(5), 894–898. Retrieved from https://ijtimes.com/index.php/ijtimes/article/view/2629

Issue

Vol. 5 No. 5 (2019): Vol. 5 No. 5: Volume 5 Issue 5 (May-2019)

Section

Articles