ANALYSIS OF OPTIMIZATION METHODOLOGY FOR SECURE CRYPTOSYSTEM USING LOW POWER VLSI DESIGN TECHNIQUES

Abstract

Security in today’s environment becomes a drastic issue in communication. For secure transmission of
data or image in open network, encryption is very important methodology. Through encryption we can prevent our
data or image from unauthorized access during transmission. In recent years many encryption methods have been
proposed and used to protect data. Image encryption and decryption using chaotic map and BB equation is one of the
best image encryption methods. VLSI architecture for the proposed algorithm is also available and is implemented in
FPGA using VHDL language in Xilinx ISE VLSI software. This implementation can be further modified with low
power VLSI criterions i.e. how the power consumption can be reduced with less delay and reduced area .To perform
the encryption process more secure and fast many ideas has been suggested and implemented. The architecture has
been implemented using different adders and it is always found that there exist tradeoffs between delay and area of
implementation. In this paper, a comparative study of different architecture used to reduce the power consumption
with the help of various adders such as carry look ahead adder, carry bypass adder, carry save adder etc has been
carried out and thus have quoted the tradeoffs between delay and area of architectures implemented. Various power
reduction techniques in digital VLSI are also discussed and implemented. With this study the best approach suitable
for different application can be easily recognized and the same can be implemented to increase the efficiency.