An High Speed Ratioed CMOS circuit design with modified Pseudo Logic Circuits

Authors

  • N. Shehanaz Adhoc Assistant Professor, JNTUA College of Engineering (Autonomous), Pulivendula
  • B.V. Sowjanya Adhoc Assistant Professor, JNTUA College of Engineering (Autonomous), Pulivendula

Keywords:

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Abstract

This paper evaluates the performance of ratioed logic circuit and conventional CMOS circuit at various
CMOS technologies. As a part of this work 4 input NAND gate is designed using conventional CMOS and pseudo
NMOS design with the help of DSCH2/ Microwind version 3.1 .The performance of both the circuits is compared
interims of dissipated power and area.

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Published

2019-05-31

How to Cite

N. Shehanaz, & B.V. Sowjanya. (2019). An High Speed Ratioed CMOS circuit design with modified Pseudo Logic Circuits. International Journal of Technical Innovation in Modern Engineering & Science, 5(15), -. Retrieved from https://ijtimes.com/index.php/ijtimes/article/view/3130

Issue

Vol. 5 No. 15 (2019): NCITEE-2019 (National Conference on Innovative Technologies in Electrical Engineering)

Section

Articles