Design Low Power 1-Bit CMOS Full Adder using DG FINFET Technique

Abstract

This paper proposes a 1-Bit CMOS full adder cell utilizing Double Gate (DG) FINFET (Fin Shaped Field Effect Transistor). The point of this paper is to diminish spillage power and spillage current of 1-bit CMOS Full Adder while keeping up the feasible introduction with less transistors are used (transistors calculate 10). A new elevated show 1- bit CMOS Full Adder in light of new rationale scheme is displayed in this paper. DG FINFET method which diminishes the procedure minor departure from 1-bit CMOS Full Adder is actualized in this paper; the legitimization of DG FINFET system is connected on 1-bit CMOS Full Adder is to diminish leakage power and leakage current. We examine We look at the utilization of DG FINFET innovation gives low spillage and superior activity by using fast and low thresh hold voltage transistors for logic cells. 1-bit CMOS Full Adder proposed design is simulated using Cadence tool at 90nm and 45nm
technology.