Comparative Analysis of Low Power MUX and DEMUX at nano scaled CMOS
Alok Kumar
Mahatma Gandhi Engineering College, Jaipur , IN
Ashwani Kumar
Mahatma Gandhi Engineering College, Jaipur , IN
Keywords: MUX, DEMUX, Low Power, Leakage Current, Cadence.
Abstract
This paper realize low power 2:1 MUX and 1:2 MUX designs using a static CMOS logic and CMOS based DEMUX. Multiplexer is a unidirectional device utilized in any application in which information must be changed from different sources to a destination. In order to suppress the degradation of signals and to increase the operation speed, we designed interconnection for the circuit; the implementation is done in VLSI technology as it has features like small size, low cost, high operating speed and low power. The circuit shows rise and fall times of about 1ns and consumes low power according to the design and number of transistor used in the circuits. The static CMOS 2:1 MUX and CMOS based 1:2 DEMUX are the most efficient design because the average power consumption is low and reduced leakage current. The designed circuits are realized in a standard 90nm process technology and uses 0.7V supply voltage. This circuit is designed and estimated results in Cadence 90nm technology.
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