Design and estimated parameter of CMOS Schmitt Trigger using Leakage Reduction Techniques
Vineet Samadhiya
PG Scholar, Department Of Electronics and communication, SRCEM Banmore, Gwalior, India , IN
Abhishek Singh Tomar
PG Scholar, Department Of Electronics and communication, SRCEM Banmore, Gwalior, India , IN
Keywords: CMOS, Schmitt Trigger, Leakage Power, Voltage Gain, Transconductance, Delay, Cadence
Abstract
In this paper high recital CMOS Schmitt trigger circuit has proposed signal shaping changeable the supply voltage with low power consumption. Schmitt trigger is input part of communication system. We have Proposed 6 Transistor Schmitt trigger using 90 nm CMOS technology and in the CMOS device for achieving enhanced performance so retain the speed, power dissipation, size, reliability of the device, applying the diverse types of technique for reducing the power consumption like SVL, AVL on CMOS Schmitt trigger using cadence tool, simulation work has been done in 90 nm technology, in this technology power consumption, Propagation Delay, Voltage gain, Transconductance have provided for CMOS Schmitt trigger circuit. AVL techniques with 6T CMOS Schmitt trigger has given high efficiency in performance in comparison to SVL technique and enhance the parameters i.e. leakage power, Transconductance, Propagation Delay and Voltage gain this type of circuit mainly use for low power processing systems.
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