Vol. 5 No. 15 (2019) ·
Articles
An High Speed Ratioed CMOS circuit design with modified Pseudo Logic Circuits
N. Shehanaz
Adhoc Assistant Professor, JNTUA College of Engineering (Autonomous), Pulivendula , IN
B.V. Sowjanya
Adhoc Assistant Professor, JNTUA College of Engineering (Autonomous), Pulivendula , IN
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Published: April 2019
Keywords: -
Abstract
This paper evaluates the performance of ratioed logic circuit and conventional CMOS circuit at various
CMOS technologies. As a part of this work 4 input NAND gate is designed using conventional CMOS and pseudo
NMOS design with the help of DSCH2/ Microwind version 3.1 .The performance of both the circuits is compared
interims of dissipated power and area.
How to Cite
N. Shehanaz, B.V. Sowjanya, “An High Speed Ratioed CMOS circuit design with modified Pseudo Logic Circuits,” International Journal of Technical Innovation in Modern Engineering & Science, vol. 5, no. 15, pp. -, April 2019.
References
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