Application Dependent fault Diagnosis of FPGA for Low power Reconfigurable Systems
Vellingiri.A
Department of Electronics and Communication Engineering KGiSL Institute of Technology, Coimbatore, India , IN
Shanmuga Priya
Department of Electronics and Communication Engineering KGiSL Institute of Technology, Coimbatore, India , IN
Keywords: Fault diagnosis, field-programmable gate array (FPGA), testing. Built-in self test (BIST)
Abstract
Application-dependent test and diagnosis of FPGAs plays a very critical role in such defect tolerance
scheme. This work is complementary to application-independent detection methods for FPGAs. This technique can
uniquely identify any single bridging, open, or stuck-at fault in the interconnect as well as any single functional fault,
a fault resulting a change in the truth table of a function, in the logic blocks. The number of test configurations for
interconnect diagnosis is logarithmic to the size of the mapped design.
The proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 × 1 multiplexer.
When used to generate test patterns for scan-based built-in self-tests, it reduces the number of transitions that occur at
the scan-chain input during scan shift operation by 50% when compared to those patterns produced by a conventional
LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. The BS-LFSR
is combined with a scan-chain-ordering algorithm that orders the cells in a way that reduces the average and peak
power (scan and capture) in the test cycle or while scanning out a response to a signature analyzer. These techniques
have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test
application time. Experimental results on ISCAS’89 benchmark circuits show up to 65% and 55% reductions in
average and peak power, respectively.
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